Sequential logic circuits are two-valued networks that produce an output that is dependent on the present input and one or more past inputs. Thus, sequential logic circuits are useful in storing binary data. Sequential logic circuits are typically classified as either synchronous or asynchronous. The behavior of synchronous sequential logic circuits is determined by the state of one or more inputs at discrete instances of time, typically latched edges of a clocking source. In contrast, the behavior of asynchronous sequential logic circuits is determined by the state of one or more inputs at any given time without regard to the clocking source. Thus, synchronous sequential logic circuits require a clocking source to control the timing of changes to the output.
A conventional flip-flop circuit is a synchronous sequential logic circuit. As such, the flip-flop is useful in storing the equivalent of one bit of data. Flip-flops are typically distinguished by their respective characteristic equation. For a given flip-flop, the characteristic equation defines the next output in terms of the one or more current inputs and the current output. In this context, the term “current” refers to the present latched edge of the clocking source and the term “next” refers to the next latched edge of the clocking source.
A conventional Delay-type (“D-type”) flip-flop includes an input data node, D, and an output data node, Q. The characteristic equation for the conventional D-type flip-flop is shown in Equation 1 below.Q(t÷1)=D(t)  (1).Thus, the output tracks the input by one latched edge of the clocking source.
In a conventional D-type flip-flop there are typically two voltage levels that govern the signaling states of the input and output. For the purposes of consistent notation, the states of the input and output are represented by Boolean values. The Boolean value “0” will represent the common or ground voltage. The Boolean value “1” will represent the operating voltage, a non-zero voltage that is process and design specific.
A truth table showing the behavior of the conventional D-type flip-flop is shown in Table 1 below.
TABLE 1D-type Flip-FlopD(t)Q(t)Q(t + 1)000101010111Time t represents the present time prior to latching the next edge of the clocking source. For example, Q(t) represents the present state of the output prior to latching the next edge of the clocking source. Q(t+1) represents the next state of the output one clock period later. Thus, the truth table implies that the next edge of the clock is latched between time t and t+1.
Returning to the example of the conventional D-type flip-flop, when the present input, D(t), is 0, and the present output, Q(t), is 0, the next output, Q(t+1), will also be 0. If the present input changes to a 1, the present output is still 0, however, the next output will be 1. If the present input changes back to a 0, the present output is now 1, and the next output will be 0. If the present input changes to a 1, the present output is still 1, and the next output will also be 1. Thus, the output is a delayed version of the input.
Because of the wide-applicability and pervasive use of the flip-flop, there is a great desire to optimize the flip-flop for use in modern applications, including high-speed microprocessor design.